Current Issue : January - March Volume : 2021 Issue Number : 1 Articles : 5 Articles
The traditional A algorithm is time-consuming due to a large number of iteration operations to calculate the evaluation function\nand sort the OPEN list. To achieve real-time path-planning performance, a hardware acceleratorâ??s architecture called A accelerator\nhas been designed and implemented in field programmable gate array (FPGA). The specially designed 8-port cache and\nOPEN list array are introduced to tackle the calculation bottleneck. The system-on-a-chip (SOC) design is implemented in Xilinx\nKintex-7 FPGA to evaluate A accelerator. Experiments show that the hardware accelerator achieves 37â??75 times performance\nenhancement relative to software implementation. It is suitable for real-time path-planning applications....
In this paper, we further study the dynamic characteristics of the Yuâ??Wang chaotic system obtained by Yu and Wang in 2012. The\nsystem can show a four-wing chaotic attractor in any direction, including all 3D spaces and 2D planes. For this reason, our interest\nis focused on multistability generation and chaotic FPGA implementation. The stability analysis, bifurcation diagram, basin of\nattraction, and Lyapunov exponent spectrum are given as the methods to analyze the dynamic behavior of this system. The\nanalyses show that each system parameter has different coexistence phenomena including coexisting chaotic, coexisting stable\nnode, and coexisting limit cycle. Some remarkable features of the system are that it can generate transient one-wing chaos,\ntransient two-wing chaos, and offset boosting. These phenomena have not been found in previous studies of the Yuâ??Wang chaotic\nsystem, so they are worth sharing. Then, the RK4 algorithm of the Verilog 32-bit floating-point standard format is used to realize\nthe autonomous multistable 4D Yuâ??Wang chaotic system on FPGA, so that it can be applied in embedded engineering based on\nchaos. Experiments show that the maximum operating frequency of the Yuâ??Wang chaotic oscillator designed based on FPGA\nis 161.212 MHz....
Reconfigurable computing is becoming ubiquitous in the form of consumer-based Internet of\nThings (IoT) devices. Reconfigurable computing architectures have found their place in safety-critical\ninfrastructures such as the automotive industry. As the target architecture evolves, it also needs\nto be updated remotely on the target platform. This process is susceptible to remote hijacking,\nwhere the attacker can maliciously update the reconfigurable hardware target with tainted hardware\nconfiguration. This paper proposes an architecture of establishing Root of Trust at the hardware\nlevel using cryptographic co-processors and Trusted Platform Modules (TPMs) and enable over the\nair updates. The proposed framework implements a secure boot protocol on Xilinx based FPGAs.\nThe project demonstrates the configuration of the bitstream, boot process integration with TPM and\nsecure over-the-air updates for the hardware reconfiguration....
Mode-division multiplexing (MDM) is an attractive solution for future on-chip networks to\nenhance the optical transmission capacity with a single laser source. A mode-division reconfigurable\noptical add/drop multiplexer (ROADM) is one of the key components to construct flexible and\ncomplex on-chip optical networks for MDM systems. In this paper, we report on a novel scheme\nof mode-division ROADM with mode-selective silicon photonic MEMS (micro-electromechanical\nsystem) switches................
Synchronous behavior can be responsible for the function or dysfunction of a neural network. To employ a memristor with\nthreshold memductance as a bidirectional synapse, a memristive synapse-connected Chay twin-neuron network is constructed.\nThis paper numerically presents the synchronous behavior for four representative firing activities in the memristive twin-neuron\nnetwork by utilizing time-domain waveforms, synchronized transition states (STSs), and mean synchronization errors (MSEs).\nIndeed, the synchronous behaviors are truly related to the coupling strength and initial condition of the memristor. Besides,\nutilizing the powerful XC7Z020 FPGA, a digitally circuit-implemented electro-neuron and the memristive synapse-connected\nChay twin-neuron network are made. Thereafter, the four representative firing activities and their STSs are experimentally\ncaptured to further confirm the numerical simulations....
Loading....